1. Field of the Invention
The present invention relates to an arithmetic correction circuit and more particularly to such a circuit for correcting the results of arithmetic operations on non-hexadecimal operands using hexadecimal arithmetic units.
2. The Prior Art
Micro-processors with hexadecimal arithmetic units have already become known, in which a correction is made for correcting the sum or difference resulting from an arithmetic operation. Typically a logic network is employed for examining the output of the hexadecimal adder, and providing for an addition of a correction factor which is equal to the difference between 16 and the base of the non-hexadecimal system which is being used. A separate logic unit is used for each four-bit word, and when eight bits are employed, the examination is cascaded. This arrangement requires a relatively large amount of hardware, so that the hardware expense is relatively high.
In other micro-processors, one of the operands has a sum added to it which is equal to the difference between 16 and the base of the non-hexadecimal system, before arithmetic operations are performed. Pseudo words or four-bit words corresponding to non-existent combinations of bits in the non-hexadecimal system can be recognized by examination of a carry bit produced during the arithmetic operation. Sometimes, when the addition of the summing factor is not appropriate, it is compensated for by addition of yet another factor corresponding to the base of the non-hexadecimal system. This system requires three commands, including two correction commands.
It is therefore desirable to provide a simpler arrangement for allowing a correction to be made when hexadecimal arithmetic units are used for performing arithmetic operations on non-hexadecimal operands.